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? semiconductor components industries, llc, 2010 november, 2010 -- rev. 18 1 publication order number: mc33364/d mc33364 critical conduction greenline t smps controller the mc33364 series are variable frequency smps controllers that operate in the critical conduction mode. they are optimized for high density power supplies requiring minimum board area, reduced component count, and low power dissipation. integration of the high voltage startup saves approximately 0.7 w of power compared to the value of the resistor bootstrapped circuits. each mc33364 features an on--board reference, uvlo function, a watchdog timer to initiate output switching, a zero current detector to ensure critical conduction operation, a current sensing comparator, leading edge blanking, a cmos driver and cycle--by--cycle current limiting. the mc33364d1 has an internal 126 khz frequency clamp. the mc33364d2 is available without an internal frequency clamp. the mc33364d has an internal 126 khz frequency clamp which is pinned out, so that the designer can adjust the clamp frequency by connecting appropriate values of resistance. features ? lossless off--line startup ? leading edge blanking for noise immunity ? watchdog timer to initiate switching ? operating temperature range --25 ? c to +125 ? c ? shutdown capability ? over temperature protection ? optional/adjustable frequency clamp to limit emi ? this is a pb--free and halide--free device ordering information device package shipping ? mc33364d1g so--8 (pb--free) 96 units / rail MC33364D1R2G 2500 units / tape & reel mc33364d2g 96 units / rail mc33364d2r2g 2500 units / tape & reel mc33364dg so--16 (pb--free) 48 units / rail mc33364dr2g 2500 units / tape & reel ?for information on tape and reel specif ications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. so--16 d suffix case 751k so--8 d1, d2 suffix case 751 16 1 8 1 pin connections mc33364d1 mc33364d2 mc33364d 18 7 6 5 2 3 4 (top view) zero current current sense voltage fb line v ref gnd gate drive v cc 116 13 12 11 10 9 2 3 4 5 6 7 8 (top view) zero current n/c current sense v ref n/c freq clamp line agnd voltage fb n/c pgnd gate drive v cc n/c marking diagrams http://onsemi.com mc33364d awlywwg 1 16 m64dx alyw g 1 8 x=1or2 a = assembly location wl = wafer lot y = year w, ww = work week gor g = pb--free package
mc33364 http://onsemi.com 2 figure 1. representative block diagram 15v/ 7.6v 15v/ var vref reset shutdown startup uvlo 1.2v/ 1.0v 10v leb watchdog timer r r s frequency clamp 0.1v level sna vcc line zcd vref fb cs fc vcc gate pgnd agnd -- + 15k 45k -- + -- + -- + 5k vref uvlo vcc thermal 15v/ 8.1v uvlo -- + vref regulator turn on turn on q figure 2. typical application circuit line zcd fc a gnd pgnd drive vcc vref fb cs input ac voltage output voltage mc33364d rsense r1 r2
mc33364 http://onsemi.com 3 figure 3. timing diagram in fault condition 0v 5v 15v vt (3.5 to 6v) 8.1v maximum drain current is limited to 1.15v / rsense 0a startup circuit is charging the vcc capacitor vref regulator turns on when vcc reaches 15v switching starts when vref reaches 5v switching stops when vref falls below 3.7v reference voltage, vref drain current vref falls faster than vcc since vref capacitor is much smaller than vcc capacitor supply voltage, vcc vref regulator turns off when vcc falls below 8.1 v startup circuit turns off when vcc is 15v startup circuit turns on when vcc reaches the threshold vt figure 4. timing diagram in normal condition maximum drain current is limited to 1.15v/ rsense drain current secondary side diode current criticial mode discontinous conduction mode leb vin drain voltage toff(min) output current voltage at zcd zcd is ignored during minimum off--time limit 0.7v 10v no load
mc33364 http://onsemi.com 4 pin description pin function description 1(1) zero current detect the zcd pin ensures critical conduction mode. zc d monitors the voltage on the auxiliary winding, during the demagnetization phase of the transformer , comparing it to an internal reference. the zcd sets the latch for the output driver. 3(2) current sense the current sense pin monitors the current in th e power switch by measuring the voltage across a resistor. leading edge blanking is utilized to prev ent false triggering. the voltage is compared to a resistor divider connected to the voltage feedbac k pin. a 110 mv voltage off--set is applied to compensate the natural optocoupler saturation voltage. 4(3) voltage feedback the voltage feedback pin is typi cally connected to the collector of the optocoupler for feedback from the isolated secondary output. the feedback is connected to the v ref pinviaa5kresistor providing bias for the external optocoupler. 6(4) v ref the v ref pin is a buffered internal 5.0 v reference with undervoltage lockout. 8(na) frequency clamp the frequency clamp pin ensures a minimum off--time value, typically 6.9 m s. it prevents the mosfet from restarting within a fixed (33364d 1) or adjustable (33364d) delay. the minimum off--time is disabled in the 33364d2. therefor e the maximum switching frequency cannot exceed 1/(t on +t offmin ). 9(5) agnd this pin is the ground for the internal ci rcuitry excluding the gate drive stage. 10 (5) pgnd this pin is the ground for the gate drive stage. 11 (6) gate drive the gate drive is the output to drive the gate of the power mosfet. 12 (7) v cc provides the voltage for all internal circ uitry including the gate drive stage and v ref . this pin has undervoltage lockout with hysteresis. 16 (8) line the line pin provides the initial power to the v cc pins. internally the line pin is a high voltage current source, eliminating the need for an external startup network. note: for further information please ref er to the following application notes; an1594: critical conduction mode, flyback s witching power supply using the mc33364. an1681: how to keep a flyback switch--mode power supply stable with a critical--mode controller. maximum ratings (t a =25 ? c, unless otherwise noted.) rating symbol value unit power supply voltage (operating) v cc 16 v line voltage v line 700 v current sense, compensation, voltage feedback, restart delay and zero current input voltage v in1 --1.0to+10 v zero current detect input i in ? 5.0 ma restart diode current i in 5.0 ma power dissipation and thermal characteristics d1 and d2 suffix, plastic package case 751 maximum power dissipation @ t a =70 ? c p d 450 mw thermal resistance, junction--to--air r ja 178 ? c/w d suffix, plastic package case 751b--05 maximum power dissipation @ t a =70 ? c p d 550 mw thermal resistance, junction--to--air r ja 145 ? c/w operating junction temperature t j 150 ? c operating ambient temperature t a --25 to +125 ? c storage temperature range t stg --55 to +150 ? c stresses exceeding maximum ratings may dam age the device. maximum ratings are stres s ratings only. functional operation above the recommended operating conditions is not impli ed. extended exposure to stresses above the re commended operating conditions may affect device reliability. note: esd data available upon request.
mc33364 http://onsemi.com 5 electrical characteristics (v cc = 15.5 v, for typical values t a =25 ? c, for min/max values t j =--25to125 ? c) characteristic symbol min typ max unit voltage reference reference output voltage (i out =0ma,t j =25 ? c) v ref 4.90 5.05 5.20 v line regulation (v cc =10vto20v) reg line -- 2.0 50 mv load regulation (i out =0mato5.0ma) reg load -- 0.3 50 mv maximum v ref output current i o -- 5 -- ma reference undervoltage lockout threshold v th -- 4.5 -- v zero current detector input threshold voltage (v in decreasing) v th 0.9 1.0 1.1 v hysteresis (v in decreasing) v h -- 200 -- mv input clamp voltage -- high state (i det =3.0ma) v ih 9.0 10.33 12 v input clamp voltage -- low state (i det =--3.0ma) v il -- 1 . 1 --0.75 0.5 current sense comparator input bias current (v cs =0to2.0v) i ib -- 0 . 5 0.02 0.5 m a built in offset v io 50 108 170 mv feedback pin input range v fb 1.1 1.24 1.4 v feedback pin to output delay t dly 100 232 400 ns drive output source resistance (drive = 0 v, v gate =v cc -- 1 . 0 v ) r oh 10 36 70 sink resistance (drive = v cc ,v gate =1.0v) r ol 5 11 25 output voltage rise time (25% -- 75%) (c l =1.0nf) t r -- 67 150 ns output voltage fall time (75% -- 25%) (c l =1.0nf) t f -- 28 50 ns output voltage in undervoltage (v cc =7.0v,i sink =1.0ma) v o(uv) -- 0.01 0.03 v leading edge blanking delay to current sense comparator input t phl(in/out) -- 250 -- ns (v fb =2.0v,v cs =0vto4.0vstep,c l =1.0nf) thermal shutdown shutdown (junction temperature increasing) hysteresis (junction te mperature decreasing) t sd t h -- -- 180 50 -- -- ? c timer watchdog timer t dly 200 360 700 m s undervoltage lockout startup threshold (v cc increasing) v th(on) 14 15 16 v minimum operating voltage after turn--on (v cc decreasing) v shutdown 6.5 7.6 8.5 v frequency clamp internal fc function (pin open) f max 104 126 145 khz internal fc function (pin grounded) f max 400 564 800 khz frequency clamp input threshold v th(fc) 1.89 1.95 2.01 v frequency clamp control current range (sink) i control 30 70 110 m a dead time (fc pin = 1.7 v) t d 3.5 5.0 6.5 m s total device line startup current (v line =50v)(v cc =v th(on) -- 1 . 0 v ) i line 5.0 8.5 12 ma restart delay time t dly 100 ms line pin leakage (v line = 500 v) i line 0.5 32 70 m a line startup current (v cc =0v,v line =50v) i line 6.0 10 12 ma v cc dynamic operating current (50 khz, c l =1.0nf) i cc 1.5 2.75 4.5 ma v cc off state consumption (v cc =11v) i cc off 300 544 800 m a
mc33364 http://onsemi.com 6 10 resistor (k ) 0 100 1000 -- 5 5 500 t dly , watchdog time delay ( s) t a , ambient temperature ( ? c) ? 450 400 350 300 --25 0 25 50 75 100 125 v cc =15v figure 5. drive output waveform figure 6. watchdog timer delay versus temperature 25 output voltage (v) 5.0 m s/div 20 15 10 0 -- 5 . 0 4.0 6.0 i cc , supply current (ma) v cc , supply voltage (v) circuit of figure 12 t a =25 ? c 4.0 2.0 0 6.0 8.0 10 12 14 16 figure 7. supply current versus supply voltage 0.01 1000 r ja(t) , thermal resistance ? t, time (s) ? junction--to--air ( c/w) 100 10 0.1 1.0 10 100 figure 8. transient thermal resistance dsuffix 16 pin soic figure 9. minimum off--time versus timing resistor on the fc pin 5 10 20 40 v cc =14v c l = 1000 pf t a =25 ? c 30 5.0 15 0 current sense voltage feedback voltage -- 0 . 4 1.0 2.5 3.5 5.0 figure 10. feedback voltage versus current sense voltage -- 0 . 2 0 0.4 0.6 0.2 0.5 1.5 3.0 4.0 2.0 4.5 0.8 1.0 1.2 1.4 6.0 5.5 dsuffix 16 pin soic t a =25 ? c v cc =15v 25 30 35 minimum off--time ( m s) f c -- t o -- v r e f f c -- t o -- g n d
mc33364 http://onsemi.com 7 operating description introduction the mc33364 series represents a variable--frequency current--mode critical--conduction solution with integrated high voltage startup and protection circuitry to implement an off--line flyback converter for modern consumer electronic power supplies. different frequency clamp options offer different customized needs. this device series includes an integrated 700 v very high--voltage (vhv) start--up circuit. thus, it is possible to design an application with universal input voltage from 85 vac to 265 vac without any additional startup circuits or components. the critical conduction feature offers some advantages. first, the mosfet turns on at zero current and the diode turns off at zero current. the zero current reduces these turn--on and turn--off switching losses. it also reduces the electro--magnetic interface (emi) of the smps and a less expensive rectifier can be used. second, by preventing the smps from entering the discontinuous conduction mode (dcm), the peak mosfet drain current is limited to only twice the average input current. it needs a smaller and less expensive mosfet. third, by preventing the smps from entering the continuous conduction mode (ccm), the flyback topology transfer function stays first--order and its feedback compensation network is considerably simplified. it also maximizes the power transfer by the flyback transformer to its 1/2 l i 2 limits. a description of each of the functional blocks is given below. the representative block diagram and typical application circuit are in figure 1 and figure 2. line, v cc , startup circuit and reference voltage the line pin is capable of a maximum 700 v so that it is possible to connect this pin directly to the rectified high--voltage alternating current (ac) input for minimizing the number of external components. there is a startup circuit block that regulates voltage from the line pin to the v cc pin in an abnormal situation. in normal conditions, the auxiliary winding powers up the v cc and this startup circuit is opened and saves approximate 0.7 w of power compared to the resistor bootstrapped circuits. in normal operation, the auxiliary winding powers up the v cc voltage. this voltage is a constant value between the uvlo limits (7.6 v and 15 v). it is further regulated to a constant 5 v reference voltage v ref for the internal circuitry usage. as long as the v cc voltage is between 7.6 v and 15 v, it means the auxiliary winding can provide voltage as in normal condition. the device recognizes that there is no fault in the circuit and the device remains in the normal operation status. however, when the auxiliary winding cannot power up v cc ,thev cc voltage will reach its uvlo limit. the device recognizes that it is an abnormal situation (such as startup or output short--circuited). the v cc voltage is not constant in this case. figure 3 shows the timing diagram in a fault condition. there are three under--voltage lock--out (uvlo) thresholds with respect to v cc . the upper threshold is 15 v. when this limit is reached, the startup circuit block turns off and v cc declines due to power consumption of the circuitry. the startup circuit block turns on when v cc reaches 7.6 v and if v ref is higher than 3.7 v. it is the second threshold of v cc .ifv ref is smaller than 3.7 v, the startup circuit will turn on when v cc reaches a temperature dependent value v t ranging between 3.5 v and 6 v. it is the last threshold of v cc . this temperature dependent threshold is lower when temperature is higher so that it takes a longer time to restore the v cc . it is a protection feature, which allows more dead time for cooling in high temperature condition. there is an uvlo in the v ref regulator block. when v cc falls below typical 8.1 v in abnormal situation, the v ref regulator block stops. v ref and v cc collapses due to power consumption of the circuitry. when v ref collapses to below 3.7 v, the device cannot provide the drive output and makes a dead time. this dead time is designed for minimal power transfer in the abnormal conditions. the dead time ends when v cc reaches 15 v after reaching the uvlo limit v t (3.5 to 6 v). reaching v t enables the startup circuit block, charging up the v cc capacitor again. when v cc reaches 15 v again, the v ref regulator block turns on and allows the output to work again. it is recommended to put a 0.1 uf capacitor on v ref pin for stability of the voltage buffer. the v cc capacitor is relatively larger than this 0.1 uf capacitor, making a longer v cc charging time from v t to 15 v and a longer dead time in the abnormal or fault conditions. zero current detect to achieve critical conduction mode, mosfet conduction is always initiated by sensing a zero current signal from the zero current detect (zcd) pin. the zcd pin indirectly monitors the inductor current by sensing the auxiliary winding voltage. when the voltage falls below a threshold of 1.0v, the comparator resets the rs latch to turn the mosfet on. there is 200 mv of hysteresis built into the comparator for noise immunity and to prevent false tripping. there are 10 v and 0.7 v clamps in the zcd pin for protection. an external resistor is recommended to limit the input current to 2 ma to protect the clamps. watchdog timer a watchdog timer block is added to the device to start or restart the drive output when something goes wrong in the zcd. when the inductor current reaches zero for longer than approximate 410 ms, the timer reset the rs latch and that turns the mosfet on.
mc33364 http://onsemi.com 8 current sense and feedback regulation current--mode control is implemented with the current sense (cs) pin and feedback (fb) pin. the fb pin is internally pulled up with a 5 kohm resistor from the 5 v v ref . there is a resistor divider circuit and a 0.1 v offset in this functional block. the following equation describes the relation between the voltages of the fb and cs pins, v fb and v cs respectively. v cs(max) = v fb M 4 ? 0.1 v when the output is short circuited, there is no feedback signal from the opto coupler and the fb pin is opened. it gives v fb = 5 v and the maximum voltage of the cs pin is 1.15 v. when the voltage exceeds 1.15 v, the current sense comparator turns on and terminates the mosfet conduction. it stops current flowing through the sense resistor (r sense ) and hence the sense resistor limits the maximum mosfet drain current by the following equation. maximum drain current = 1.15 M r sense when the output voltage is too high, the fb pin voltage is pulled down by the opto coupler current and the duty ratio is reduced. the output voltage is then regulated. there is a leading edge blanking (leb) circuit with 250 ns propagation delay to prevent false triggering due to parasitics in the cs pin. it makes a minimum on--time of the mosfet (t on(min) ). thermal shutdown there is a thermal shutdown block to prevent overheating condition and protect the device from overheating. when temperature is over 180 _ c, the drive output and startup circuit block are disable. the device resumes operation when temperature falls below 130 _ c. gate drive output the ic contains a cmos output driver specifically designed for direct drive of power mosfet. the drive output typical rise and fall times are 50 ns with a 1.0 nf load. unbalanced source and sink eliminates the need for an external resistor between the device drive output and the gate of the external mosfet. additional internal circuitry has been added to keep the drive output in a sinking mode whenever the uvlo is active. this characteristic eliminates the need for an external gate pull--down resistor. frequency clamp options the drawback of critical conduction mode is variable switching frequency. the switching frequency can increase dramatically to hundreds of khz when the output current is too low or vanishes. it is a big problem when emi above 150 khz is concerned. frequency clamp (fc) is an optional feature in the device to limit the upper switching frequency to nominal 126 khz by inserting a minimum off--time (t off(min) ). when a minimum off--time is inserted, the maximum frequency (f max ) limit is set. f max = 1 t on(min) + t off(min) the smps is forced to operate in dcm when the maximum frequency is reached. the minimum off--time is immediately counted after the driving signal goes low. if the zcd signal comes within this minimum off--time, the zcd information is ignored until the minimum off--time expires. the next zcd signal starts the mosfet conduction. there are three available fc options: mc33364d -- adjustable minimum off--time by external resistor, mc33364d1 -- 6.9 us fixed minimum off--time, and mc33364d2 -- no minimum off--time (fc disable). the mc33364d has a fc pin, which can vary the minimum off--time (or the maximum frequency) externally in figure 11. if the fc pin is opened, the minimum off--time is fixed at 6.9 us. if the fc pin is grounded, the clamp is disabled, and the smps will always operate in critical mode. it is generally not recommended to sink or source more than 80 ua from the fc pin because high currents may cause unstable operation. vref fc fc gnd increase toff decrease toff fc fc gnd toff = 6.9us toff = 0us (fc disable) figure 11. frequency clamp setting
mc33364 http://onsemi.com 9 application information design example design an off--line flyback converter according to the following requirements: output power: 12 w output: 6.0 v @ 2 amperes input voltage range: 90 vac -- 270 vac, 50/60 hz the operation for the circuit shown in figure 12 is as follows: the rectifier bridge d1--d4 and the capacitor c1 convert the ac line voltage to dc. this voltage supplies the primary winding of the transformer t1 and the startup circuit in u1 through the line pin. the primary current loop is closed by the transformer?s primary winding, the tmos switch q1 and the current sens e resistor r7. the resistors r5, r6, diode d6 and capacitor c4 create a snubber clamping network that protects q1 from spikes on the primary winding. the network consisting of capacitor c3, diode d5 and resistor r1 provides a v cc supply voltage for u1 from the auxiliary winding of the transformer. the resistor r1 makes v cc more stable and resistant to noise. the resistor r2 reduces the current flow through the internal clamping and protection zener diode of the zero crossing detector (zcd) within u1. c3 is the decoupling capacitor of the supply voltage. the resistor r3 can provide additional bias current for the optoisolator?s transistor. the diode d8 and the capacitor c5 rectify and filter the output voltage. the tl431, a programmable voltage reference, drives the primary side of the optoisolator to provide isolated feedback to the mc33364. the resistor divider consisting of r10 and r11 program the voltage of the tl431. the resistor r9 and the capacitors c7 and c8 provide frequency compensation of the feedback loop. resistor r8 provides a current limit for the opto coupler and the tl431. since the critical conduction mode converter is a variable frequency system, the mc33364 has a built--in special block to reduce switching frequency in the no load condition. this block is named the ?frequency clamp? block. mc33364 used in the design example has an internal frequency clamp set to 126 khz. however, optional versions with a disabled or variable frequency clamp are available. the frequency clamp works as follows: the clamp controls the part of the switching cycle when the mosfet switch is turned off. if this ?off--time? (determined by the reset time of the transformer?s core) is too s hort, then the frequency clamp does not allow the switch to turn--on again until the defined frequency clamp time is reached (i.e., the frequency clamp will insert a dead time). there are several advantages of the mc33364?s startup circuit. the startup circuit includes a special high voltage switch that controls the path between the rectified line voltage and the v cc supply capacitor to charge that capacitor by a limited current when the power is applied to the input. after a few switching cycles the ic is supplied from the transformer?s auxiliary winding. after v cc reaches the undervoltage lockout threshold value, the startup switch is turned off by the undervoltage and the overvoltage control circuit. because the power supply can be shorted on the output, causing the auxiliary voltage to be zero, the mc33364 will periodically start its startup block. this mode is named ?hiccup mode?. during this mode the temperature of the chip rises but remains protected by the thermal shutdown block. during the power supply?s normal operation, the high voltage internal mosfet is turned off, preventing wasted power, and thereby, allowing greater circuit efficiency. since a bridge rectifier is used, the resulting minimum and maximum dc input voltages can be calculated: v in(min) dc = 2 ? xv in(min) ac = ? 2 ? ? ? 90 vac ? = 127 v v in( m ax) dc = 2 ? xv in( m ax) ac = ? 2 ? ? ? 270 vac ? = 382 v the maximum average input current is: i in = p out nv in(min) = 12 w 0.8 ? 127 v ? = 0.118 a where n = estimated circuit efficiency. a tmos switch with 600 v avalanche breakdown voltage is used. the voltage on the switch?s drain consists of the input voltage and the flyback voltage of the transformer?s primary winding. there is a ringing on the rising edge?s top of the flyback voltage due to the leakage inductance of the transformer. this ringing is clamped by the rcd network. design this clamped wave for an amplitude of 50 v below the avalanche breakdown of the tmos device. add another 50 v to allow a safety margin for the mosfet. then a suitable value of the flyback voltage may be calculated: v flbk = v tmos ? v in(max) ? 100 v = 600 v ? 382 v ? 100 v = 118 v since this value is very close to the v in(min) ,set: v flbk = v in(min) = 127 v the v flbk value of the duty cycle is given by: ? max = v flbk v flbk + v in(min) = 127 v [ 127 v + 127 v ] = 0.5 the maximum input primary peak current: i ppk = 2i in ? max = 2.0 ? 0.118 a ? 0.5 = 0.472 a choose the desired minimum frequency f min of operation to be 70 khz. after reviewing the core siz ing information provided by a core manufacturer, a ee core of size about 20 mm was chosen. siemens? n67 magnetic material is used, which corresponds to a philips 3c85 or tdk pc40 material.
mc33364 http://onsemi.com 10 the primary inductance value is given by: l p = ? max v in(min) ? i ppk ? ? f min ? = 0.5 ? 127 v ? ? 0.472 a ?? 70 khz ? = 1.92 mh the manufacturer recommends for that magnetic core a maximum operating flux density of: b max = 0.2 t the cross--sectional area a c of the ef20 core is: a c = 33.5 mm 2 the operating flux density is given by: b max = l p i ppk n p a c from this equation the number of turns of the primary winding can be derived: n p = l p i ppk b max a c the a l factor is determined by: a l = l p n 2 p = l p ? b max a c ? 2 ? l p ? i ppk ? 2 ? = ? 0.2 t ? ? 33.5e--6m 2 ? 2 ? .00192 h ? ? 0.472 a ? 2 = 105 nh from the manufacturer?s catalogue recommendation the core with an a l of 100 nh is selected. the desired number of turns of the primary winding is: n p = ? l p a l ? 1 M 2 = ? ? 0.00192 h ? ? 100 nh ? ? 1 M 2 = 139 turns the number of turns needed by the 6.0 v secondary is (assuming a schottky rectifier is used): n s = ? v s + v fwd ? ? 1? ? max ? n p ? ? max ? v in(min) ? ? = ? 6.0 v + 0.3 v ? ? 1 ? 0.5 ? 139 ? 0.5 ? 127 v ? ? = 7 turns the auxiliary winding to power the control ic is 16 v and its number of turns is given by: naux = (v aux + v fwd )(1 ?? max)n p ? ? max(v in(min) ) ? = (16 v + 0.9 v)(1 ? 0.5)139 [0.5(127 v)] = 19 turns the approximate value of rectifier capacitance needed is: c1 = t off (i in ) v ripple = (5 m sec)(0.118 a) 50 v = 11.8 m f where the minimum ripple frequency is 2 times the 50 hz line frequency and t off , the discharge time of c1 during the haversine cycle, is assumed to be half the cycle period. because we have a variable frequency system, all the calculations for the value of the output filter capacitors will be done at the lowest frequency, since the ripple voltage will be greatest at this frequency. when selecting the output capacitor select a capacitor with low esr to minimize ripple from the current ripple. the approximate equation for the output capacitance value is given by: c5 = i out (f min )(v rip ) = 2a (70 khz)(0.1 v) = 286 m f determining the value of the current sense resistor (r7), one uses the peak current in the predesign consideration. since within the ic there is a limitation of the voltage for the current sensing, which is set to 1.2 v, the design of the current sense resistor is simply given by: r7 = v cs i ppk = 1.2 v 0.472 a = 2.54 2.2 the error amplifier function is provided by a tl431 on the secondary, connected to the primary side via an optoisolator, the moc8102. the voltage of the optoisolator collector node sets the peak current flowing through the power switch during each cycle. this pin will be connected to the feedback pin of the mc33364, which will directly set the peak current. starting on the secondary side of the power supply, assign the sense current through the voltage--sensing resistor divider to be approximately 0.25 ma. one can immediately calculate the value of the lower and upper resistor: r lower = r11 = v ref (tl431) i div = 2.5 v 0.25 ma = 10 k r upper = r10 = v out ? v ref (tl431) i div = 6.0 v ? 2.5v 0.25 ma = 14 k the value of the resistor that would provide the bias current through the optoisolator and the tl431 is set by the minimum operating current requirements of the tl431. this current is minimum 1.0 ma. assign the maximum current through the branch to be 5 ma. that makes the bias resistor value equal to: r bias = r s = v out ? [v ref (tl431) + v led ] i led = 6.0 v ? [2.5v + 1.4v] 5.0 ma = 420 430
mc33364 http://onsemi.com 11 the moc8102 has a typical current transfer ratio (ctr) of 100% with 25% tolerance. when the tl431 is full--on, 5 ma will be drawn from the transistor within the moc8102. the transistor should be in saturated state at that time, so its collector resistor must be r collector = v ref ? v sat i led = 5.0 v ? 0.3 v 5.0 ma = 940 since a resistor of 5.0 k is internally connected from the reference voltage to the feedback pin of the mc33364, the external resistor can have a higher value r ext = r3 = (r int )(r collector ) (r int ) ? (r collector ) = (5.0 k)(940) 5.0 k ? 940 = 1157 1200 this completes the design of the voltage feedback circuit. in no load condition there is only a current flowing through the optoisolator diode and the voltage sense divider on the secondary side. the load at that condition is given by: r noload = v out (i led + i div ) = 6.0 v (5.0 ma + 0.25 ma) = 1143 the output filter pole at no load is: f ph = 1 (2 r noload c out ) = 1 (2 )(1143)(300 m f) = 0.46 hz in heavy load condition the i led and i div is negligible. the heavy load resistance is given by: r heavy = v out i out = 6.0 v 2.0 a = 3.0 the output filter pole at heavy load of this output is f ph = 1 (2 r heavy c out ) = 1 (2 )(3)(300 m f) = 177 hz the gain exhibited by the open loop power supply at the high input voltage will be: a = ? v in max ? v out ? 2 ns ? (v in max )(v error )(np) ? = ? 382 v ? 6.0 v ? 2 (7) (382 v)(1.2 v)(139) = 15.53 = 23.82 db the maximum recommended bandwidth is approximately: f c = fs min 5 = 70 khz 5 = 14 khz the gain needed by the error amplifier to achieve this bandwidth is calculated at the rated load because that yields the bandwidth condition, which is: gc = 20 log ? f c f ph ? ? a = 20 log ? 14 khz 177 ? ? 23.82 db = 14.14 db the gain in absolute terms is: a c = 10 (gc M 20) = 10 (14.14 M 20) = 5.1 now the compensation circuit elements can be calculated. the output resistance of the voltage sense divider is given by the parallel combination of resistors in the divider: r in = r upper || r lower = 10 k || 14 k = 5833 r9 = (ac) (r in ) = 29.75 k 30 k c8 = 1 ? 2 (a c )(r in )(f c ) ? = 382 pf 390 pf the compensation zero must be placed at or below the light load filter pole: c7 = 1 ? 2 (r9) (f pn ) ? = 11.63 m f 10 m f
mc33364 http://onsemi.com 12 figure 12. circuit in the design example startup reference restart delay watchdog timer frequency clamp thermal shutdown line gate pgnd cs fc fb vref zcd vcc vcc uvlo ref uvlo zcd vref buffer 4.7 15 / 7.6 10v 1.2/1.0 1.25v 45k 15k 4k 10v 0.1v 2v current sense leb vcc 5k r r s q emi filter 85 to 265 vac c1 10 m f 400v d1 1n4006 mtd1n60 q1 t1 r4 470 (optional) r10 14 k r8 430 c8 330 pf 6.0 v 2.0 a c7 10 m f c4 1 m f 1 2 4 5 u2 tl431 2 1 3 d5 1n4934 d6 mur160 d8 mbr340 r1 56 r6 47 k r9 39 k r11 10 k agnd d2 d3 d4 r7 2.2 c3 20 m f c10 0.1 m f r5 47 k c5 300 m f u3 moc8102 + r2 22 k mc33364d r3
mc33364 http://onsemi.com 13 r3 47k mc33364 figure 13. critical conduction mode flyback converter the described critical conduction mode flyback converter has the following performance and maximum ratings: output power 12w output 12v @ 1amp max input voltage range 90vac -- 270vac j1 line j2 gnd 2 1 1 d1 s380 3 10uf 8 7 1 3 4 2 6 5 gnd vref fb line vcc zcd gate cs 10uf 220 r1 d2 1n4148 21 c4 r4 47k c5 1nf d3 murs160t3 1 r5 2.2 34 q1 mtd1n60 mbrd360 d4 5 4 moc8102 u3 r6 2k7 r7 820 r8 18k 300uf c6 1 23 r9 4k7 100nf c9 u1 u2 j3 j4 1 1 --vout tl431 +vout 9 7 t1 4 2 r2 100k 0.1uf 400v 1 2 converter test data test conditions results line regulation v in = 120vac to 240vac, i out =0.8a v = 50mv load v in = 120vac, i out = 0.2a to 0.8a v = 40mv v in = 240vac, i out = 0.2a to 0.8a v = 40mv output ripple v in = 120vac, i out =0.8a v = 290mv v in = 240vac, i out =0.8a v = 24mv efficiency v in = 120vac, i out =0.8a = 78.0% v in = 240vac, i out =0.8a = 79.4% power factor v in = 120vac, i out =0.8a pf = 0.491 v in = 240vac, i out =0.8a pf = 0.505 figure 14. load regulation 120v figure 15. load regulation 240v vout iout vout iout ch1: 2.0v/div 2.0 msec/div ch1: 2.0v/div 2.0 msec/div ch2: 200ma/div ch2: 200mv/div
mc33364 http://onsemi.com 14 c3 0.1 m f j1 line d1 b250r c1 f1 t0.2a 8line 7v cc 1zcd gate 6 cs 2 4 v ref gnd 5 c2 20 m f r1 220 d3 1n4148 r5 47 k r6 47 k c4 1.0 nf q1 mtd1n60e r4 2.2 u1 mc33364d1 54 1 2 j2 543 2 7 9 d6 murs320t3 d7 1n4148 r7 100 d8 b2x84c5v1lt1 c6 1.0 m f r8 4.7 k c5 100 m f u2 mc33341 8 7 6 54 3 2 1 v cc gnd v s csb do cmp cta csa r12 82 k r11 10 k r13 22 k r3 22 k r10 0.25 r9 100 c7 33 nf 3 fb figure 16. universal input battery charger 12 10 m f 400 v t1 d5 murs 160t3 12 5.1 v t1 = 139 turns #28 awg, primary winding 2 -- 3 7 turns, bifilar 2 x #26 awg, output winding 9 -- 7 19 turns #28 awg, auxiliary winding 4 -- 5 on philips ef20--3c85 core gap for a primary inductor of 1.92 mh. output 12 v @ 0.8 amp max input voltage range 90 -- 270 vac, 50/60 hz u3 moc8102
mc33364 http://onsemi.com 15 package dimensions so--8 d1, d2 suffix case 751--07 issue aj seating plane 1 4 5 8 n j x45 _ k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751--01 thru 751--06 are obsolete. new standard is 751--07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0808 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 -- x -- -- y -- g m y m 0.25 (0.010) -- z -- y m 0.25 (0.010) z s x s m ____ 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 ? mm inches ? scale 6:1 *for additional information on our pb--free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
mc33364 http://onsemi.com 16 package dimensions so--16 d suffix case 751k--01 issue o notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. dim a min max min max inches 9.80 10.00 0.368 0.393 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0707 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 ____ 18 9 16 g p c k 14 x d seating plane j r _ m _ -- a -- -- b -- m 0.25 (0.010) b s f x45 -- t -- s a m 0.25 (0.010) b s t on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further noti ce to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation speci al, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performa nce may vary over time. all operating parameters, including ?typicals? must be validated for each custo mer application by customer?s techni cal experts. scillc does not conve y any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical impl ant into the body, or other applications intended to support or sustain life, or fo r any other application in which the failure of the scillc product could create a situation wher e personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unaut horized application, buyer shall indemnify and hold scillc and its offic ers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or in directly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such clai m alleges that scillc was negligent regarding the design or manufactur e of the part. scillc is an equal opportunity/affirmative action employer. this literature is subj ect to all applicable c opyright laws and is not for resale in any manner. mc33364/d greenline is a trademark of motorola, inc. publication ordering information n. american technical support : 800--282--9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81--3--5773--3850 literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303--675--2175 or 800--344--3860 toll free usa/canada fax : 303--675--2176 or 800--344--3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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